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82562ET 10/100 Mbps Platform LAN Connect (PLC)
Networking Silicon
Datasheet
Product Features
s s s s s s s s
IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction LAN Connect Interface
s s s s s s s
Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in "unplugged mode" (less than 50 mW) Automatic detection of "unplugged mode" 3.3 V device 48-pin Shrink Small Outline Package
Revision 1.3 March 2003
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2003, Intel Corporation * Other brands and names are the property of their respective owners.
Datasheet
Networking Silicon -- 82562ET
Revision History
Revision 1.3 1.2 Revision Date March 2003 October 2001 Description Added product ordering code in Section 1.0. Removed confidential status. * Removed sections: "Physical Layer Interface Functionality" and "Platform LAN Connect". * Changed "Electrical and Timing Specifications" section to "Voltage and Temperature Specifications" and removed timing specifications. Advance Information Datasheet release (Intel Confidential). * On cover page, replaced Boundary Scan Support with XOR tree mode support. Added bullet for LAN Connect I/F. * Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but replaced EM with ET in diagram. * Pg. 11, removed Figure 4, "NRZ to MLT-3 Encoding Diagram". * Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0. Advance Information Datasheet release (Intel Secret). * Modified Table 1 "82562ET Hardware Configuration" to add one row for XOR Tree and include column for comments. * Updated the descrition of the Activity LED signal in Section 3.6, "LED Pins". * Revised Section 3.7, "Miscellaneous Control Pins" to reflect references to Table 1 "82562ET Hardware Configuration". * Updated Section 4.0, "Voltage and Temperature Specifications". * Replaced diagrams in Section 5.1, "Package Information". * Corrected Figure 4 "NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect correct signal transitions. * Removed "10BASE-T Error Detection and Reporting" section since the 82562 does not do 10BASE-T error reporting. Initial release.
1.1
June 2000
1.0
May 2000
0.6
Nov. 1999
0.55
Sept. 1999
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82562ET -- Networking Silicon
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Datasheet
Networking Silicon -- 82562ET
Contents
1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 2.0 3.0 Overview ............................................................................................................... 1 Features ................................................................................................................ 1 References ............................................................................................................ 1
82562ET Architectural Overview........................................................................................ 3 82562ET Signal Descriptions ............................................................................................. 5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Signal Type Definitions ......................................................................................... 5 Twisted Pair Ethernet (TPE) Pins .........................................................................5 External Bias Pins ................................................................................................ 5 Clock Pins ............................................................................................................ 6 Platform LAN Connect Interface Pins....................................................................6 LED Pins .............................................................................................................. 7 Miscellaneous Control Pins .................................................................................. 7 Power and Ground Connections .......................................................................... 8
4.0
Voltage and Temperature Specifications ...........................................................................9 4.1 4.2 Absolute Maximum Ratings................................................................................... 9 DC Characteristics ............................................................................................... 9 4.2.1 X1 Clock DC Specifications ..................................................................... 9 4.2.2 LAN Connect Interface DC Specifications .............................................10 4.2.3 LED DC Specifications .......................................................................... 10 4.2.4 10BASE-T Voltage and Current DC Specifications ............................... 10 4.2.5 100BASE-TX Voltage and Current DC Specifications ..........................11
5.0
Package and Pinout Information ...................................................................................... 13 5.1 5.2 Package Information ........................................................................................... 13 Pinout Information ............................................................................................... 14 5.2.1 82562ET Pin Assignments .................................................................... 14 5.2.2 82562ET Shrink Small Outlying Package Diagram ............................... 15
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82562ET -- Networking Silicon
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Datasheet
Networking Silicon -- 82562ET
1.0
1.1
Introduction
Overview
The Intel(R) 82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the current platform LAN connect interface.
1.2
Features
* * * * * * * * * * * * * * *
IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR Tree mode support for board testing 3-port LED support (speed, link and activity) 10BASE-T auto-polarity correction Diagnostic loopback mode 1:1 transmit transformer ratio support Low power (less than 300 mW in active transmit mode) Reduced power in "unplugged mode" (less than 50 mW) Automatic detection of "unplugged mode" 3.3 V device 48-pin Shrink Small Outline Package Platform LAN connect interface support
1.3
References
* IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers
* 82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation * LAN Connect Interface Specification, Intel Corporation
Datasheet
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82562ET -- Networking Silicon
1.4
Product Code
The product ordering code for the 82562ET is: DA82562ET.
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Datasheet
Networking Silicon -- 82562ET
2.0
82562ET Architectural Overview
The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1 provides a block diagram of the 82562ET architecture.
Figure 1. 82562ET Block Diagram
Digital Equalizer Adaptation Equalizer & BLW correction MDI/MDI-X CRS/Link 10 Detection Transmit DAC 10/100 AutoNegotiation Bias & BandGap Voltage Circuit Clock Generator Control Registers Digital Clock Recovery (100) Digital Clock Recovery (10) 100Base-TX PCS
Port LED Drivers
LILED ACTLED SPEEDLED
RDN/RDP
LAN_RSTSYNC
10Base-T PCS LAN Connect Interface
3 3
LAN_TXD[2:0] LAN_RXD[2:0] LAN_CLK
TDN/ TDP
X1
Crystal 25 MHz
X2
The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document describes the architecture of the device in all modes of operation. Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test Execute (ISOL_EX), define the general operation of the device. Table 1 shows the pin settings for the different modes of operation. Table 1. 82562ET Hardware Configuration
Mode of Operation Normal operating mode Isolate mode (Tri-state and full power-down mode) 1 XOR Tree 1 0 0 0 1 1 1 TESTEN 0 ISOL_TCK 0 ISOL_TI 0 ISOL_EX 0 Comments The ISOL_TCK, ISOL_TI, and ISOL_EX pins can remain floating. The device is in tri-state and power-down mode. The device is in tri-state and the fully powered down. The XOR Tree is used for board testing and tri-state mode.
0
1
1
1
NOTE: Combinations not shown in Table 1 are reserved and should not be used.
Datasheet
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82562ET -- Networking Silicon
Figure 2. 82562ET Solution Overview
VRM
Procesor
Clock
ADDR
DATA
CTRL
Termination ADDR CTRL DATA
MCH
2 RIMM Modules
IDE Primary PCI Connector 1 PCI Connector 2 IDE Secondary PCI Control Bus ICH2 USB Port 1 USB USB Port 2 PCI Address/Data Bus PCI Connector 3 Parallel UltraDMA/33
AMC97 Audio/ Modem
AC97 Link
Control Address/Data LPC Bus SIO 82562ET PLC
82550 LAN Controller
Keyboard Mouse
Floppy
Game Conn
Serial 1
4
Datasheet
Networking Silicon -- 82562ET
3.0
3.1
82562ET Signal Descriptions
Signal Type Definitions
Type I O I/O MLT B DPS APS Name Input Output Input/Output Multi-level analog I/O Bias Digital Power Supply Input pin to the 82562ET. Output pin from the 82562ET. Multiplexed input and output pin to and from the 82562ET. Multi-level analog pin used for input and output. Bias pin used for ground connection through a resistor or an external voltage reference. Digital power or ground pin for the 82562ET. Description
Analog Power Analog power or ground pin for the 82562ET. Supply
3.2
Twisted Pair Ethernet (TPE) Pins
Pin Name TDP TDN Pin Number 10 11 Type MLT Description Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer.
RDP RDN
15 16
MLT
3.3
External Bias Pins
Pin Name RBIAS10 RBIAS100 Pin Number 4 5 B B Type Description Bias Reference Resistor 10. This pin should be connected to a 549 pull-down resistor.a Bias reference Resistor 100. This pin should be connected to a 619 pull-down resistor.b
a. 549 for RBIAS10 is only a recommended value and should be fine tuned for various designs. b. 619 for RBIAS100 is only a recommended value and should be fine tuned for various designs.
Datasheet
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82562ET -- Networking Silicon
3.4
Clock Pins
Pin Name X1 Pin Number 46 I Type Description Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Otherwise, X1 is driven by an external metaloxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better.
X2
47
O
3.5
Platform LAN Connect Interface Pins
Pin Name LAN_CLK Pin Number 39 Type O Description LAN Connect Clock. The LAN Connect Clock is driven by the 82562ET on two frequencies depending on operation speed. When the 82562ET is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: * Reset. When this pin is asserted beyond one LAN Connect clock period, the 82562ET uses this signal Reset. To ensure reset of the 82562ET, the Reset signal should remain active for at least 500 seconds. Synchronize. When this pin is activated synchronously, for only one LAN Connect clock period, it is used to synchronize the MAC and PHY on LAN Connect word boundaries.
LAN_ RSTSYNC
42
I
*
LAN_ TXD[2:0]
45, 44, 43
I
LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562ET. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to LAN_CLK. LAN Connect Receive Data. The LAN Connect receive pins are used to transfer data from the 82562ET to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK.
LAN_ RXD[2:0]
37, 35, 34
O
6
Datasheet
Networking Silicon -- 82562ET
3.6
LED Pins
Pin Name LILED# Pin Number 27 Type O Description Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either mode, the LILED is asserted. Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. The flicker rate depends on the activity load. The individual address LED control bit (Word A hexadecimal, bit 4) in the ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in Wake on LAN (WOL) mode. 0 = In WOL mode, the ACTLED is activated by the transmission and reception of broadcast and individual address match packets. 1 = In WOL mode, the ACTLED is activated by the transmission and reception of individual address match packets only. This bit is configured by the OEM and is activated by a transmission and reception of individual address match packets. SPDLED# 31 O Speed LED. The LED is active low and the Speed LED signal indicates the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX operation and off in 10BASE-T mode.
ACTLED#
32
O
3.7
Miscellaneous Control Pins
Pin Name ADV10 Pin Number 41 I Type Description Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562ET advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562ET advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. ISOL_TCK 30 I Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal pull-down resistor. ISOL_TI 28 I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal pull-down resistor.
Datasheet
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82562ET -- Networking Silicon
Pin Name ISOL_TEX
Pin Number 29 I
Type
Description Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1). In the manufacturing test mode, it places the command that was entered through the TI pin in the instruction register. Note: ISOL_TEX has an internal pull-down resistor.
TOUT TESTEN
26 21
O I
Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. Test Enable. The Test Enable pin is used to enable test mode and should be pulled down to VSS to allow XOR Tree test mode.
3.8
Power and Ground Connections
Pin Name VCC VCCP VCCA VCCA2 VCCT VSS VSSP VSSA VSSA2 VCCR VSSR Pin Number 1, 25 36, 40 2, 7, 9, 12, 14, 17 8, 13, 18 DPS 24, 48 33, 38 3 6 19, 23 20, 22 APS APS Analog Power. Analog Ground. These pins should not be isolated from the main digital. Digital Ground. These pins should be connected to the main digital ground. Type DPS Description Digital 3.3 V Power. These pins should be connected to the main digital power supply.
8
Datasheet
Networking Silicon -- 82562ET
4.0
4.1
Voltage and Temperature Specifications
Absolute Maximum Ratings
Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 135 C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C Supply Voltage with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 3.45 V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562ET device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4.2
Table 2.
DC Characteristics
General DC Specifications
Symbol VCC T Parameter Supply Voltage Temperature Minimum/Maximum Case Temperature 10/100Mbps (transmitter on) Reduced Power Auto-Negotiation Condition Min 3.0 0 300 50 200 Typical 3.3 Max 3.45 85 Units V C mW mW mW Notes
P
Power Consumption
4.2.1
Table 3.
X1 Clock DC Specifications
X1 Clock DC Specifications
Symbol VIL VIH IILIH CI Parameter Input Low Voltage Input High Voltage Input Leakage Currents Input Capacitance 0 < V IN < VCC 2.0 10 8 Condition Min Typical Max 0.8 Units V V A pF 1 Notes
NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only.
Datasheet
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82562ET -- Networking Silicon
4.2.2
Table 4.
LAN Connect Interface DC Specifications
LAN Connect Interface DC Specifications
Symbol VCCJ VIL V IH IIL VOL VOH CIN Parameter Input/Output Supply Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage Input Pin Capacitance 0 < VIN < VCCJ IOUT = 1500 A IOUT = -500 A 0.9VCCJ 8 Condition Min 3.0 -0.5 0.6VCCJ Typical Max 3.45 0.3VCCJ VCCJ + 0.5 10 0.1VCCJ Units V V V A V V pF 1 Notes
NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only.
4.2.3
Table 5.
LED DC Specifications
LED DC Specifications
Symbol VOLLED VOHLED Parameter Output Low Voltage Output High Voltage Condition IOUT = 10 mA IOUT = -10 mA 2.4 Min Typical Max 0.7 Units V V Notes
4.2.4
Table 6.
10BASE-T Voltage and Current DC Specifications
10BASE-T Transmitter
Symbol VOD10 Parameter Condition Min 2.2 Typical Max 2.8 Units V Notes 1
Output Differential RL = 100 Peak Voltage
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN.
10
Datasheet
Networking Silicon -- 82562ET
Table 7.
10BASE-T Receiver
Symbol RID10 VIDA10 Parameter Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage DC 5 MHz f 10 MHz Condition Min 10 Typical Max Units K Notes 1
585
3100
mV
VIDR10 VICM10
5 MHz f 10 MHz
300
mV
VCC/2
V
NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN.
4.2.5
Table 8.
100BASE-TX Voltage and Current DC Specifications
100BASE-TX Transmitter
Symbol VOD100 Parameter Condition Min 0.95 Typical 1.0 Max 1.05 Units V Notes 1
Output Differential RL = 100 Peak Voltage
NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. RL is the resistive load measured across the transmit differential pins, TDP and TDN.
Table 9.
100BASE-TX Receiver
Symbol RID100 VIDA100 Parameter Input Differential Resistance Input Differential Accept Peak Voltage Input Differential Reject Peak Voltage Input Common Mode Voltage VCC/2 DC Condition Min 10 Typical Max Units K Notes 1
500
1200
mV
VIDR100 VICM100
100
mV
V
NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN.
Datasheet
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82562ET -- Networking Silicon
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Datasheet
Networking Silicon -- 82562ET
5.0
5.1
Package and Pinout Information
Package Information
The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are shown in Figure 3. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office.
Figure 3. Dimension Diagram for the 82562ET 48-pin SSOP
Datasheet
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82562ET -- Networking Silicon
5.2
5.2.1
Pinout Information
82562ET Pin Assignments
Table 10. 82562ET Pin Assignments
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name VCC VCCA VSSA RBIAS10 RBIAS100 VSSA2 VCCA2 VSS VCCT TDP TDN VCCT Pin Number 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name VSS VCCT RDP RDN VCCT VSS VCCR VSSR TESTEN VSSR VCCR VSS Pin Number 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VCC TOUT LILED ISOL_TI ISOL_TEX ISOL_TCK SPDLED ACTLED VSSP LAN_RXD0 LAN_RXD1 VCCP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name LAN_RXD2 VSSP LAN_CLK VCCP ADV10
LAN_RSTSYNC
LAN_TXD0 LAN_TXD1 LAN_TXD2 X1 X2 VSS
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Datasheet
Networking Silicon -- 82562ET
5.2.2
82562ET Shrink Small Outlying Package Diagram
Figure 4. 82562ET Pin Out Diagram
VCC (DPS) VCCA (APS) VSSA (APS) RBIAS10 (B) RBIAS100 (B) VSSA2 (APS) VCCA2 (APS) VSS (DPS) VCCT (APS) TDP (MLT) TDN (MLT) VCCT (APS) VSS (DPS) VCCT (APS) RDP (MLT) RDN (MLT) VCCT (APS) VSS (DPS) VCCR (APS) VSSR (APS) TESTEN (I) VSSR (APS) VCCR (APS) VSS (DPS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40
VSS (DPS) X2 (O) X1(I) LAN_TXD2 (I) LAN_TXD1 (I) LAN_TXD0 (I) LAN_RSTSYNC ADV10 (I) VCCP (DPS) LAN_CLK (O) VSSP (DPS) LAN_RXD2 (O) VCCP (DPS) LAN_RXD1 (O) LAN_RXD0 (O) VSSP (DPS) ACTLED# (O) SPDLED# (O) ISOL_TCK (I) ISOL_TEX (I) ISOL_TI (I) LILED# (O) TOUT (O) VCC (DPS)
82562ET PIN DIAGRAM SSOP48 Rev 1.0 Top View
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Datasheet
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